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INTERFACE
ISOLATION
SERIAL NUMBER
RECORDS
REGISTERS

Tag decodes
 

The two data bytes are encoded in bcd representing the major / minor revision level of the vendor and the oem respectively. This record is optional but normally appears as the first data record after the serial number.
 

These variable length strings are optional and apply in context. They are present solely for human readable information. When present before a logical device record it applies to the card as a whole. When present after any logical device record it applies to that device.
 

Both of these are variable length records and are optional. The first three bytes (if present) are encoded ascii as per the encoded serial number described elsewhere for the short form.
 
 

The encoded 4 byte id has same structure as the 4 byte encoded_serial id.

The reg byte(s) define supported features of the interface in pnp registers 30 to 3F.  (reg-hi is optional and assumed to be zero by default)

bit 0  Device capable of taking part in boot process
bit 1  Device supports I/O range check register
bit 2  Device supports reserved register 0x32
............
bit 15  Device supports reserved register 0x3F

Reserved registers 32 to 3F have no meaning.

Occurrence of this tag marks the beginning of specific information about a logical device on that card. Subsequent record tags contain resource information about that device.
 

Encoded as per the serial number, this field is optional and only present in a device context.
 

Eight possible configurations are allocated to each device (not all are declared).

This tag delineates the beginning of each configuration. Resource records follow each startdep.

The type byte if present defines the type of configuration data that follows.

0 preferred, or autoconfig
1 acceptable (default)
2 functional

Up to two IRQ records can be recieved per device-configuration. (startdep)

The two-byte [irqbits] represent the irqs from  0 to 15 that can be used with this device (irq 2 is not useable).

The type field if present defines

bit 0  High true, edge sensitive interrupt (default)
bit 1  Low true, edge sensitive interrupt
bit 2 High true, level sensitive interrupt
bit 3 Low true, level sensitive interrupt

Type is an information byte, there is nothing choosable about it.
 

Up to two dma records can be recieved per device-config (startdep)

The single byte dmabits defines the usable dma channels that can be used on this device. bit 4 is not useable.

type is the dma capability defined as follows

0SSWCMbbb

SS DMA channel speed

0 compatible mode
1  type A
2 type B
3 type F

bbb

0 8bit only
1 both
2 16bit only

8 separate io address records can be recieved per start record.

aa=nonzero 16bit address lines else 10bit address lines

[min] and [max] declare the range of base io addresses that can be used for this device.

iosize

declares the number of io addresses used after and including the base address. A value of zero means 256.

alignment

Means the next address that could be used as a base, if the min address is not suitable.

Typically, a soundblaster would have a minimum base address of 0x220, a maximum base address of 0x280, an alignment of 0x20 and a size of 16

This would result in one, of the four following possible selections.

0x220 -> 0x22F
0x240 -> 0x24F
0x260 -> 0x26F
0x280 -> 0x28F
 

Fixed io is a 'no choice' declaration.
 

This defines a block of memory in 256 byte chunks. The total memory range declared is within a 64k page as defined by the page byte.

Bit[7] Reserved and must be 0
Bit[6] Memory is an expansion ROM
Bit[5] Memory is shadowable.
Bits[4:3] Memory control Status
 00 8-bit memory only
 01 16-bit memory only
 10 8- and 16-bit supported.
 11 Reserved
 Bit[2] Support type Status
 1 decode supports high address
  0 decode supports range length.
  Bit[1] Cache support type Status
 1 read cacheable, write-through
   0 non-cacheable.
 Bit[0] Write status
  1 writeable
 0 non-writeable (ROM)

size defines the amount of 256 byte chunks used, and step defines the beginning base address that can be stepped. Thus, for an ethernet card

00 D0 D0 00 0000 0001

would indicate a base memory address at 0: D000 to 0: D0FF
 

page: as above
long minimum address
long maximum address
long base alignment
long range

fixed 32 mem
page as above
long base address
long range

These blocks of io, dma, memory and irq tags are repeated for each start record encountered for the device (up to 8 times).
 

The end of device configuration data for this device is deliniated by this tag. Subsequent records define some other device. There is only one endep for each device. Start records deliniate themselves.
 

This is the end of all records for the card. This check sum is generated such that adding it to the sum of all the data bytes will produce a zero sum.
 

Vendor defined desctiptors which are unused.